1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and particularly to a multi-bank, non-volatile semiconductor memory device having a plurality of banks. More particularly, the present invention relates to a flash memory (background operation (BGO) flash memory) having background operation function that allows, while an internal operation such as erasing/programming operation is being performed with respect to one bank, data to be read out from another bank.
2. Description of the Background Art
FIG. 25 schematically shows an entire configuration of a conventional BGO flash memory. Referring to FIG. 25, the conventional BGO flash memory includes a plurality of banks B#1-B#4. These banks B#1-B#4, each addressable independently of others, have essentially an identical configuration. Thus, in FIG. 25, reference characters for internal components of only bank B#1 are representatively denoted.
Banks B#1-B#4 each include: a memory array MA having a plurality of non-volatile memory cells arranged in rows and columns; a pre-decoder PD that pre-decodes an internal address signal from an address buffer 901; a row decoder RD that decodes an internal row address (pre-decoded) signal from pre-decoder PD and selects an addressed row in memory array MA; a column decoder CD that decodes an internal column address signal (pre-decoded signal) from pre-decoder PD and generates a column select signal for selecting an addressed column in memory array MA; a Y gate YG for selecting a column in memory array MA according to the column select signal from column decoder CD; and a sense amplifier SA that senses and amplifies data on the column selected by Y gate YG.
Each of these banks B#1-B#4 is further provided with a write circuit for transmitting a voltage corresponding to write data to a selected memory cell (bit line) in a write mode. The write circuit, however, is not shown in FIG. 25 for simplification of the drawing.
The non-volatile semiconductor memory device further includes: a bank pointer 903 that decodes a bank address signal included in the internal address signal from address buffer 901 and generates a bank designating signal for selectively activating banks B#1-B#4; an internal control circuit 900 that takes in an externally supplied command CMD according to a control signal CTL and generates various internal control signals for performing an operating mode designated by the command CMD; a data buffer 913 that takes in externally supplied data according to control signal CTL and generates internal write data, and externally outputs the data in a read mode; a write data buffer 904 provided corresponding to banks B#1 and B#3 and latches the data supplied from data buffer 913 in a write mode; an erase/program verify circuit 905 provided corresponding to banks B#1 and B#3 and detects, in the erasing/programming operation, whether the erasing and programming operations are performed accurately; a write data buffer 906 provided corresponding to banks B#2 and B#4 and latches the internal write data from data buffer 913; and an erase/program verify circuit 907 for detecting, in the erasing/programming operation of bank B#2 or B#4, whether the erasing or the programming is performed accurately in the selected bank.
The write data in write data buffer 904 is supplied to the write circuits (not shown) of banks B#1 and B#3, and an internal voltage corresponding to the write data is transmitted to an internal data line (bit line). Likewise, write data buffer 906 supplies the write data to the write circuits (not shown) of banks B#2 and B#4, and a voltage corresponding to the write data is transmitted to a selected column of bank B#2 or B#4.
In erasing/programming operation, the erasing and programming operations differ for different types of flash memories. In a NOR type flash memory, the erasing operation is an operation of lowering a threshold voltage of a transistor in a memory cell, which is done by drawing electrons out of a floating gate of the memory cell transistor. In a DINOR type flash memory, the erasing operation is an operation of raising the threshold voltage of the memory cell transistor by injecting electrons into the floating gate of the memory cell transistor. Likewise, in the programming operation, the threshold voltage of the memory cell transistor is raised in the NOR type flash memory, whereas the threshold voltage is lowered in the DINOR type flash memory.
In the erasing/programming operation, internal control circuit 900 performs, according to a verify result designating signal from erase/program verify circuit 905 or 907, the erasing/programming operation repeatedly until the erasure or program is carried out accurately. In addition, internal control circuit 900 causes address buffer 901 to take in an externally supplied address signal AD according to command CMD and to generate, in the internal operation, an internal control address signal according to the address taken in.
Address buffer 901 generates both an internal address signal corresponding to the externally supplied address signal AD and the internal control address signal generated under the control of internal control circuit 900. Bank pointer 903 can generate, according to the internal address signal and the internal control address signal from address buffer 901, both an internal operating bank designating signal and a bank designating signal corresponding to the external address signal. By generating both the internal address signal corresponding to the external address signal AD and the internal control address signal generated under the control of internal control circuit 900, it becomes possible, while the internal operation such as erasing/programming operation is being performed in one bank, to access another bank for reading out memory cell data.
The non-volatile semiconductor memory device further includes: a register circuit 908 that stores a device production code (ID code) specific to the device; a register circuit 909 that stores common flash interface (CFI) codes (normally 32 kinds of data) such as an erase cycle time and storage capacity; a register circuit 910 that stores status data indicating operating states of the banks; a register circuit 911 that stores lock bits indicating presence/absence of lock in banks B#1-B#4 on a block basis; and an output switching circuit 912 that selects, according to a read mode switching signal RSW from internal control circuit 900, one of data Di read out from these register circuits 908-911 and banks B#1-B#4, for application to data buffer 913.
In this non-volatile semiconductor memory device, during the time where the erasing/programming operation is being performed in one bank, it is possible to access another bank or status register circuit 910 to read out necessary data. Such function (capability) that enables, while an internal operation is being performed in one bank, data to be read out from a circuit (the status register circuit or a bank) other than the bank currently subject to the internal operation, is called background operation (BGO) function (capability). Generally in a non-volatile semiconductor memory device, while data reading is done at a speed as high as 50 ns (nano seconds) to 100 ns, the erasing/programming operation requires a relatively long time on the order of 2 xcexcs to 5 s. By enabling the access to one bank or the status register circuit during the erasing/programming operation of another bank, wait time of the system decreases, thereby improving processing efficiency of the system.
To perform such internal operation and data reading on a bank basis, each bank is provided with a sense amplifier SA.
FIG. 26 schematically shows a configuration of address buffer 901 shown in FIG. 25. Referring to FIG. 26, address buffer 901 includes: a NAND circuit 901a that receives external address signal AD and an address buffer activating signal ABE; an inverter 901b that inverts the output signal of NAND circuit 901a to generate an intermediate address signal ADi; two-stage, cascaded inverters 901c and 901d that receive intermediate address signal ADi output from inverter 901b to generate an external reading address signal AE; and an address latch 901e that receives the internal control address signal ICAD from internal control circuit 900 and intermediate address signal ADi, takes in a received address signal according to an external address latch enable signal EALE and an internal control address latch enable signal IALE, and generates an internal control address signal AI.
Address buffer activating signal ABE is activated according to control signal CTL (chip enable signal /CE, write enable signal /WE, and output enable signal /OE). External address latch enable signal EALE is activated when command CMD is externally supplied. Internal control address latch enable signal IALE is activated upon execution of the internal operation. Internal control address signal ICAD is generated in data reading in a page mode, for example, by internally updating the address signal in a sequential manner, with external address signal AD being a leading address. Upon erasing/programming operation (in the case where the erasing is to be performed on the block basis), a block address signal is generated from external address signal AD for performing an erasing on the block basis.
FIG. 27 shows a configuration of address latch 901e shown in FIG. 26. Referring to FIG. 27, address latch 901e includes: a transfer gate 920a that is rendered conductive in response to activation (an H level) of external address latch enable signal EALE, to pass intermediate address signal ADi; a transfer gate 920b that is rendered conductive upon activation (an H level) of internal control address latch enable signal IALE to pass internal control address signal ICAD; a NAND circuit 920c having a first input receiving an address signal supplied from one of transfer gates 920a and 920b, and a second input receiving a reset signal ZRST; an inverter 920e that inverts the output signal of NAND circuit 920c to generate internal control address signal AI (for use in internal control); and an inverter 920d that inverts the output signal of NAND circuit 920c to feed back the inverted signal to the first input of NAND circuit 920c. Reset signal ZRST is activated (or driven to an L level) upon completion of an internal operation or upon reception of a new command. When reset signal ZRST is activated to the L level, all the bits of internal control address signal AI are set to an L level.
From address latch 901e, either the internal control address signal corresponding to external address signal AD or the internal control address signal ICAD processed by internal control circuit 900 is selected and output as the address signal AI for the internal operation.
More specifically, as shown in FIG. 28, upon the application of command CMD, external address signal AD is also applied at the same time. External address signal AD and command CMD are latched by internal control circuit 900 at a rise of control signal CTL. According to the control signal CTL (/CE, /WE, /OE) upon application of the command CMD, address buffer activating signal ABE is activated, and intermediate address signal ADi is generated according to external address signal AD. Then, according to the decode result of command CMD, external address latch enable signal EALE is activated, and transfer gate 920a is rendered conductive. Internal control address signal AI (AD0) is thus generated according to external address signal AD (intermediate address signal ADi).
When the page mode operation or the erasing/programming operation is designated by command CMD, internal control address signal ICAD is updated under the control of the internal control circuit 900. In such internal operation, internal control address latch enable signal IALE is activated under the control of internal control circuit 900, and transfer gate 920b is rendered conductive. Thus, internal control address signal AI is changed to internal control address signal ICAD (0) applied from internal control circuit 900.
Address signals AE and AI from address buffer 901 shown in FIG. 26 are both applied to bank pointer 903 shown in FIG. 25. According to these address signals AE and AI, bank pointer 903 generates bank designating signals for specifying the banks for external data reading and for internal operation, respectively.
FIG. 29 shows a configuration of bank pointer 903 shown in FIG. 25. Bank pointer 903 includes: gate circuits 903a-903d that decode most significant two bits AE less than m:mxe2x88x921 greater than  of external reading address signal bits AE less than m:0 greater than  to generate bank designating signals AEB1-AEB4, respectively; and gate circuits 903e-903h that generate bank designating signals AIB1-AIB4 for control of internal operation according to most significant two bits AI less than m:mxe2x88x921 greater than  of internal control address signal bits AI less than m:0 greater than . Address signals AE and AI each are a signal of (m+1) bits. The number of banks is four, and an address of two bits is used for specifying a bank.
Gate circuit 903a drives bank designating signal AEB1 to an active state of an H level when address bits AE less than m greater than  and AE less than mxe2x88x921 greater than  are both at an L level. Gate circuit 903b drives bank designating signal AEB2 to an active state of an H level when address bit AE less than m greater than  is at an L level and address bit AE less than mxe2x88x921 greater than  is at an H level. Gate circuit 903c drives bank designating signal AEB3 to an active state of an H level when address bit AE less than m greater than  is at an H level and address bit AE less than mxe2x88x921 greater than  is at an L level. Gate circuit 903d drives bank designating signal AEB4 to an active state of an H level when address bits AE less than m greater than  and AE less than mxe2x88x921 greater than  are both at an H level. These bank designating signals AEB1-AEB4 designate banks B#1-B#4, respectively.
Gate circuit 903e drives bank designating signal AIB1 to an active state of an H level when address bits AI less than m greater than  and AI less than mxe2x88x921 greater than  are both at an L level. Gate circuit 903f drives bank designating signal AIB2 to an active state of an H level when address bit AI less than m greater than  is at an L level and address bit AI less than mxe2x88x921 greater than  is at an H level. Gate circuit 903g drives bank designating signal AIB3 to an active state of an H level when address bit AI less than m greater than  is at an H level and address bit AI less than mxe2x88x921 greater than  is at an L level. Gate circuit 903h drives bank designating signal AIB4 to an active state of an H level when address bits AI less than m greater than  and A less than mxe2x88x921 greater than  are both at an H level. Bank designating signals AIB1-AIB4 designate banks B#1-B#4, respectively.
As shown in FIG. 29, in bank pointer 903, bank designating signals AEB1-AEB4 for external reading are generated based on external reading address signal AE, and bank designating signals AIB1-AIB4 for internal operation are generated based on internal control address signal AI. Thus, the internal operation and the external data reading operation can be performed in parallel.
FIG. 30 schematically shows a configuration of a bank activating unit. Referring to FIG. 30, bank B#i (i=1 to 4) is activated upon activation of a bank specifying signal BPi that is output from an OR circuit 925 receiving bank designating signals AEBi and AIBi. When bank specifying signal BPi is activated, address decode circuitry (pre-decoder PD, column decoder CD and row decoder RD) are activated in bank B#i, and a memory cell selecting operation is performed according to the address signal supplied.
FIG. 31 schematically shows a configuration of sense amplifier SA in one bank. Referring to FIG. 31, sense amplifier SA includes: a sense circuit 926 that is activated in response to activation of a sense amplifier activating signal ZSE and senses and amplifies data supplied from the Y gate; an internal read circuit 927 that is activated upon activation of an external read activating signal RDE and transmits the data sensed and amplified by sense circuit 926 to the data buffer; and a verify read circuit 928 that is activated in response to activation of a verify read activating signal VRDE and supplies the data sensed and amplified by sense circuit 926 to the erase/program verify circuit.
External read activating signal RDE is generated based on bank designating signal AEB, while verify read activating signal VRDE is generated based on internal operating bank designating signal AIB. More specifically, when bank designating signal AEBi is activated, internal read circuit 927 associated with bank B#i is activated, and selected memory cell data is supplied to the data buffer for externally reading out the data. When internal operating bank designating signal AIBi is activated, the operation of bank B#i is controlled by internal control circuit 900. When erasing and programming are performed and the erase/program verifying operation is performed, verify read activating signal VRDE is activated for verification of the erase/program. Sense activating signal ZSE is activated under the control of internal control circuit 900, when either one of bank designating signals AEBi and AIBi is activated.
FIG. 32 schematically shows configurations of internal control circuit 900 and output switching circuit 912 shown in FIG. 25. Referring to FIG. 32, internal control circuit 900 includes: a command decoder 900a that takes in externally supplied command CMD according to control signal CTL, and generates a signal designating an internal operation designated by the command CMD; an internal control signal generating circuit 900b that generates various internal control signals according to the internal operation designating signal from command decoder 900a; a coincidence detecting circuit 900c that detects coincidence/non-coincidence of bank designating signals AEB (AEB1-AEB4) and AIB (AIB1-AIB4) at the time of the internal operation; and a status data control circuit 900d that generates, upon detection of the coincidence by coincidence detecting circuit 900c, status data of the designated bank under the control of internal control signal generating circuit 900b, and writes the generated data to status register 910.
Internal control signal generating circuit 900b generates, in accordance with the operating mode designating signal from command decoder 900a and the coincidence/non-coincidence detecting signal from coincidence detecting circuit 900c, a main sense amplifier activating signal ZSEM, an internal read activating signal RDEM, and a verify read activating signal VRDEM, an output mode switching signal RSW. These activating signals ZSEM, RDEM and VRDEM are main control signals. Logical products of these signals with the bank designating signal are taken to generate sense amplifier activating signal ZSE, external read activating signal RDE and verify read activating signal VRDE, respectively, for the designated bank.
When a bank undergoing an internal operation is designated by an externally supplied address, internal control signal generating circuit 900b activates status data control circuit 900d, generates data indicating the status (progress of erasing/programming) in that bank, and writes the generated data via status data control circuit 900d to status data register 910. At the time of detection of the coincidence, internal control signal generating circuit 900b sets read mode switching signal RSW to a state allowing selection of status data register 910. Upon command application, an operation according to the command is performed.
Output switching circuit 912 includes transfer gates TX1-TX4 provided corresponding to respective register circuits 908, 909, 910 and 911, and a transfer gate TX5 receiving read data Di from a selected bank. One of these transfer gates TX1-TX5 is activated according to read mode switching signal RSW. These transfer gates TX1-TX5 may be tri-state buffer circuits. Now, an operation of the circuit shown in FIG. 32 will be described with reference to the flow chart shown in FIG. 33.
Here, in FIG. 33, an operation for reading out memory cell data or data stored in a register circuit from the non-volatile semiconductor memory device will be described.
A determination is made whether a command is externally applied (step S1). When a read command for reading out data is externally supplied, first, a determination is made whether there is a bank currently subject to an internal operation (step S2). If there is no bank in progress of the internal operation, the command supplied is decoded, and an operation designated by the command is performed (step S8). At this time, read mode switching signal RSW is also set according to the command supplied (step S9). Thereafter, data (memory cell data or data in a register circuit) is selected by output switching circuit 912 according to the command supplied, and the selected data is externally output via data buffer 913.
In step S2, if it is determined that there is a bank currently under the internal operation (by making a determination that there is an internal operating bank designating signal AIB in an active state), a further determination is made whether the address signal simultaneously supplied with the command designates the bank currently in progress of the internal operation by coincidence detecting circuit 900c (step S3). If a bank other than the bank subject to the internal operation is designated, the command CMD is a memory cell reading command. In response, an array read mode is set (step S6), memory cell selection and data reading are performed according to the externally supplied address signal (step S7), and the memory cell data is externally output via data buffer 913 (step S10).
In step S3, if the bank currently subject to the internal operation is designated by the externally supplied address signal, coincidence detecting circuit 900c detects such coincidence, and status data control circuit 900d generates status data. This data indicating the status of the bank undergoing the internal operation is written and stored in status register circuit 910. Thereafter, read mode switching signal RSW is forcibly set to the state for selection of status register circuit 910, and transfer gate TX3 is rendered conductive (step S5). The status data stored in status data register circuit 910 is then externally output via data buffer 913 (step S10).
Note that the array read mode is set in step S6. In this case, an operation of externally supplying the signals designating data reading (/OE, /CE in an active state) along with the address signal may be performed (the array read mode is set in advance). In other words, there is a case where data reading is performed simply by activating output enable signal /OE.
Thus, as shown in FIG. 32, external reading bank designating signal AEB and internal operating bank designating signal AIB are generated to activate the banks designated by these bank designating signals. Accordingly, it is possible to perform, during an internal operation in one bank, data reading in another bank.
In a BGO flash memory, a background operation is possible in which, during an internal operation in one bank, another bank is accessed for data reading. In the case of the prior art, however, operating modes are limited to the one for reading data from another bank, or the one for reading out the status data of the bank in progress of the internal operation. This is because the original object of the background operation is to improve access efficiency by allowing, during the erasing/programming period of one bank, reading of data stored in another bank. Thus, in the case described above, data cannot be read out from register circuits 908, 909 and 911 during the background operation, or more specifically, it is not possible to perform an operation of reading out, e.g., a block lock bit to check a rewritable region in each bank. This limits the application of the background operation function. This poses a problem that the application of the background operation function is limited.
In addition, to set the operation content of read, a command must be externally supplied to re-set the state of read mode switching signal RSW. In this case, after the application of the read command, output enable signal /OE must be activated to designate the data output, so that two cycles are required. Thus, the internal data reading takes time. (This poses another problem that the internal data reading takes a relatively long time.)
More specifically, once the state of read mode switching signal RSW is set by a read command, such state of the signal RSW is maintained continuously. To sequentially read out the CFI code, block lock bit and status data, it is necessary to apply, for each operation, a command designating reading of the corresponding data, and thereafter, it is also necessary to activate output enable signal /OE for each data output. Thus, the necessary internal data cannot be read out at high speed. The same applies to memory cell data reading.
Further, in a normal flash memory without the BGO capability, register circuits storing various kinds of specific data are provided. In this case, during the internal operation in which erasing or programming is internally performed, an externally output readylbusy signal is set at a busy state. Only when the ready/busy signal attains a ready state, data such as status data can be read out. In this case as well, to read out specific data in a specific internal register circuit, it is necessary to apply a command specifying the register circuit, and after a command latching/decoding operation, the output enable signal (included in control signal CTL) must be set to an active state. Thus, fast reading of such specific data is not possible.
An object of the present invention is to provide a non-volatile semiconductor memory device allowing reduction of time required for reading out necessary data.
Another object of the present invention is to provide a non-volatile semiconductor memory device capable of reading out any desired data externally at high speed.
A further object of the present invention is to provide a non-volatile semiconductor memory device with excellent usability.
The non-volatile semiconductor memory device according to a first aspect of the present invention includes: a circuit generating an operating mode designating signal that designates one operating mode from a plurality of operating modes according to a prescribed bit of an externally supplied address signal; and an operation control circuit generating a control signal for performing the operating mode designated according to the operating mode designating signal.
The non-volatile semiconductor memory device according to another aspect of the present invention includes: circuitry for detecting a change of a value of a prescribed bit in successive multi-bit address signals; and circuitry for setting an operating mode, upon detection of the change of the value of the prescribed bit in the address signals, according to the prescribed bit of a latter address signal of the successive multi-bit address signals.
Preferably, the non-volatile semiconductor memory device has background operation function, and sets an operation being performed in the background operation according to the prescribed bit value of the address signal.
As the content of the read mode is determined according to the prescribed bit of the address signal, necessary data can be read out externally at high speed, with no need of application of a command.
In addition, by setting the content of read mode with a command once, it is possible to externally read out necessary data simply by changing a value of the prescribed bit of an address signal upon and/or after the execution of the internal operation. Thus, even in a time period other than that of the background operation, necessary data can be read out at high speed, an increased number of kinds of data can be externally read out, so that the usability of the device is improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.